1. Technical Field
The present invention relates to ferroelectric memory devices and electronic apparatuses. More particularly, the present invention relates to ferroelectric memory devices that perform a stable readout operation.
2. Related Art
A conventional FeRAM is described in Japanese Laid-open Patent Application 2002-100183. A ferroelectric memory described in the aforementioned Patent Document 1 is equipped with a 0-level setting circuit provided in a preceding stage of a sense amplifier, for re-setting a signal on a lower potential side among binarized signals to 0V.
However, in the conventional FeRAM described in JP 2002-100183, a high voltage is impressed to its memory cell, and therefore there is a problem in that fatigue characteristics of the ferroelectric that compose the memory cell are substantially deteriorated. Also, because its circuit structure is complex, there are problems in that the readout operation requires a long time, and the operation speed lowers.
Accordingly, it is an object of the present invention to provide ferroelectric memory devices and electronic apparatuses, which can solve the problems described above. This object is achieved by combinations of the characteristics recited in independent claims in Scope of Patent Claims. Also, dependent claims further define advantageous concrete examples of the present invention.